The operation of logic circuits in integrated circuits normally requires the switching of transistors between on and off states. Such switching generates transient signals or noise. Noise can be detected on the Vss distribution line and analyzed to provide information about the signals in the logic circuit. In other devices, such as A/D converters, noise limits the resolution of the device.
It is possible to isolate CMOS switching transients from the Vssl distribution by the use of an on-chip shunt voltage regulator. The shunt voltage regulator operates from +5 V to -5 V while the CMOS logic operates from +5 V (Vdd) to ground (Vss). The shunt voltage regulator maintains a predetermined constant current flow between +5 V and Vss. CMOS logic draws current from the shunt regulator to satisfy its instantaneous needs and current not used by the CMOS logic is shunted from +5 V to Vss. The current used by the CMOS logic and current shunted are added to form an essentially constant current. The constant value of current must be set to more than any demand required by CMOS logic or noise will be detected (and hence, information). Noise reduction on the power distribution system is impressive using this technique, with noise reduction of at least -120dB. However, this technique requires a power level of more than twice the peak power consumed by the CMOS logic and an additional power supply voltage is required (-5 V).
Another possible solution to the noise problem is complementary node switching, sometimes referred to as load balancing, which produces a transition in dummy logic elements that is in opposition to the primary logic node. Dummy loads are required to fully complement the noise profile of the primary node. We discovered that the resulting Vss distribution transient noise with complementary node switching was larger than it was without using this noise control technique and gave a noise signature that permitted the extraction of data from the noise. That is an undesirable attribute for secure data communications applications. The complimentary node switching technique also required inclusion of complementary logic elements and the associated loads was very difficult to implement (if not impossible). The matching of speeds between the primary logic and its complement was not feasible. There was more noise present than when the complementary logic was not used.
Another approach for reducing the digital switching noise has been developed by Allstot, Kiaei and Zele, "Analog Logic Techniques Steer Around the Noise," IEEE Journal of Circuits & Devices, pp 18-21, September 1993. That approach uses a current steering technique that draws constant current from Vdd. The current that is dumped on the Vss distribution will see a transient current that is device parameter limited as the input transitions to a logical "1." The Iss transient may be used to determine the current-steering logic elements state level.
So, it would be desireable to have a low noise logic circuit that consumed less power than existing techniques. If the shunt voltage regulator could be eliminated, power savings (extended battery life) could be realized.